IP 集成指南¶

module chip_top (
    input  wire        clk,
    input  wire        rst_n,
    output wire        uart_tx,
    input  wire        uart_rx
);

// UART 实例化
uart u_uart (
    .clk      (clk),
    .rst_n    (rst_n),
    .uart_tx  (uart_tx),
    .uart_rx  (uart_rx),
    .pclk     (clk_apb),
    .presetn  (rst_apb_n),
    .paddr    (paddr[7:0]),
    .pwdata   (pwdata),
    .psel     (psel_uart),
    .penable  (penable),
    .pwrite   (pwrite),
    .prdata   (prdata_uart),
    .pready   (pready_uart),
    .pslverr  (pslverr_uart)
);

endmodule