axi_master¶

模块信息¶

属性	值
文件名	`axi_master.v`
模块名	`axi_master`
代码行数	432
版本	1.0
作者	Chip Team
日期	2026-05-07

功能说明¶

AXI4 Master Interface - Full-featured AXI4 master controller

详细说明¶

This module implements a complete AXI4 master interface with the following features: - Support for write and read transactions - Burst transfer with configurable length (1-16 beats) - Address alignment and byte strobe generation - State machine based control logic - Configurable base address for dynamic transaction initiation

架构设计¶

The module uses a 6-state FSM to manage AXI4 transactions: - IDLE: Wait for configuration enable - AW: Write address channel handshake - W: Write data channel handshake - B: Write response channel handshake - AR: Read address channel handshake - R: Read data channel handshake

参数配置¶

参数名	类型	默认值	说明
`DATA_WIDTH`	parameter	`64`	Data bus width in bits. Must be a power of 2 (32, 64, 128, 256)
`ADDR_WIDTH`	parameter	`32`	Address bus width in bits. Typically 32 or 64
`ID_WIDTH`	parameter	`4`	ID signal width for transaction identification
`BURST_LEN`	parameter	`16`	Maximum burst length (number of beats per transaction)

端口列表¶

Clock and Reset¶

端口名	方向	位宽	类型	说明
`clk`	input	1	wire	System clock input
`rst_n`	input	1	wire	Active-low asynchronous reset

寄存器映射¶

寄存器名	位宽	说明
`addr_reg`	[ADDR_WIDTH-1:0]	Address register for storing transaction address
`data_reg`	[DATA_WIDTH-1:0]	Data register for storing write data
`burst_count`	[7:0]	Burst counter: Tracks number of beats transferred
`transfer_active`	1	Transfer active flag: Indicates ongoing transaction

状态机定义¶

current_state¶

状态定义¶

状态名	值
`IDLE_STATE`	`3'b000`
`AW_STATE`	`3'b001`
`W_STATE`	`3'b010`
`B_STATE`	`3'b011`
`AR_STATE`	`3'b100`
`R_STATE`	`3'b101`
`DONE_STATE`	`3'b110`

形式验证断言 (SVA)¶

reset_idle¶

类型: property
说明: SVA: Reset Safety
覆盖目标:
Cover the case where reset is released and state is IDLE
Cover the case where reset is released and state is NOT IDLE (error)

handshake_timeout¶

类型: property
说明: SVA: Handshake Validity
覆盖目标:
Cover successful handshake within timeout
Cover timeout violation (should not occur in simulation)

response_valid¶

类型: property
说明: SVA: Response Validity
覆盖目标:
Cover OKAY response (2'b00)
Cover EXOKAY response (2'b01)
Cover SLVERR response (2'b10)
Cover DECERR response (2'b11)

注意事项¶

⚠️ The module supports both write and read transactions but processes them sequentially. Write transactions are prioritized over read transactions.

警告¶

🚨 Ensure that the burst length does not exceed the configured BURST_LEN parameter to avoid data corruption.

参考资料¶

AXI4 Specification, ARM IHI 0022E
axi_master_tb.v for testbench and verification environment

文档由 gen-rtl-docs.py 自动生成 源码路径: rtl/axi_master.v