系统框图¶

系统架构框图¶

graph TB
    subgraph CPU["CPU 核心 (RISC-V RV32IMC)"]
        CPU_CORE[CPU Core]
        I_CACHE[I-Cache 16KB]
        D_CACHE[D-Cache 16KB]
    end

    subgraph MEMORY["存储系统"]
        L2_CACHE[L2 Cache 256KB]
        SRAM[SRAM 512KB]
        ROM[ROM 512KB]
    end

    subgraph AXI_SYSTEM["AXI4 互连"]
        AXI_MASTER[AXI Master]
        AXI_SLAVE[AXI Slaves]
        INTERCONNECT[AXI Interconnect]
    end

    subgraph PERIPHERALS["外设接口"]
        UART[UART × 2]
        SPI[SPI × 2]
        I2C[I2C × 2]
        GPIO[GPIO × 32]
        TIMER[Timer × 4]
    end

    subgraph APB_SYSTEM["APB 总线"]
        APB_MASTER[APB Master]
        APB_SLAVES[APB Slaves]
    end

    CPU --> I_CACHE
    CPU --> D_CACHE
    I_CACHE --> L2_CACHE
    D_CACHE --> L2_CACHE
    L2_CACHE --> SRAM
    L2_CACHE --> ROM
    CPU --> AXI_MASTER
    AXI_MASTER --> INTERCONNECT
    INTERCONNECT --> AXI_SLAVE
    AXI_SLAVE --> APB_MASTER
    APB_MASTER --> APB_SLAVES
    APB_SLAVES --> UART
    APB_SLAVES --> SPI
    APB_SLAVES --> I2C
    APB_SLAVES --> GPIO
    APB_SLAVES --> TIMER

总线架构¶

AXI4 通道¶

APB 接口¶

时钟域¶