RTL 文件理解文档¶

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文件数：13

快速导航¶

序号	文件	模块/类数	链接
1	`if.sv`	1	查看
2	`raminfr.v`	1	查看
3	`timescale.v`	0	查看
4	`uart_debug_if.v`	1	查看
5	`uart_defines.v`	0	查看
6	`uart_receiver.v`	1	查看
7	`uart_regs.v`	1	查看
8	`uart_rfifo.v`	1	查看
9	`uart_sync_flops.v`	1	查看
10	`uart_tfifo.v`	1	查看
11	`uart_top.v`	1	查看
12	`uart_transmitter.v`	1	查看
13	`uart_wb.v`	1	查看

文件详情¶

if.sv¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/if.sv

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_if`	interface	1	0

uart_if¶

端口定义：

信号名	方向	类型	位宽	描述
`clock`	input	bit	-

内部信号：

名称	类型	位宽
`wb_addr_i`	logic	[4:0]
`wb_dat_i`	logic	[7:0]
`wb_sel_i`	bit	[3:0]
`wb_we_i`	bit	-
`wb_ack_o`	bit	-
`wb_rst_i`	logic	-
`wb_clk_i`	bit	-
`int_o`	bit	-
`baud_o`	bit	-
`stx_pad_o`	bit	-
`srx_pad_i`	bit	-
`rts_pad_o`	bit	-
`dtr_pad_o`	bit	-
`ri_pad_i`	bit	-

raminfr.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/raminfr.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`raminfr`	module	0	0	Dual-Port RAM Infrastructure

raminfr¶

Dual-Port RAM Infrastructure

Distributed RAM primitive with synchronous write and asynchronous dual-port read. Used by TX and RX FIFOs.

Parameters

aw: Address width
dw: Data width
depth: Memory depth

内部信号：

名称	类型	位宽
`ram`	reg	[data_width-1:0]
`dpo`	wire	[data_width-1:0]
`di`	wire	[data_width-1:0]
`a`	wire	[addr_width-1:0]
`dpra`	wire	[addr_width-1:0]

timescale.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/timescale.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

uart_debug_if.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_debug_if.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_debug_if`	module	0	0	32-bit Debug Interface

uart_debug_if¶

32-bit Debug Interface

Provides read-only access to internal UART signals via WISHBONE. Only available in 32-bit data bus mode.

Debug Registers

Addr	Content
0x08	{MSR, LCR, IIR, IER, LSR}
0x0C	{FCR, MCR, RF_COUNT, RSTATE, TF_COUNT, TSTATE}

内部信号：

名称	类型	位宽	说明
`wb_adr_i`	wire	[`UART_ADDR_WIDTH-1:0]
`wb_dat32_o`	reg	[31:0]

uart_defines.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_defines.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

uart_receiver.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_receiver.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_receiver`	module	0	0	UART Receiver State Machine

uart_receiver¶

UART Receiver State Machine

Implements serial data reception with configurable frame format. Detects start bit, samples data bits at baud rate, checks parity, and verifies stop bit. Stores received data with error flags in RX FIFO.

States

IDLE -> REC_START -> REC_PREPARE -> REC_BIT[xN] -> [REC_PARITY] -> REC_STOP -> PUSH -> IDLE

Error Detection

Framing error: stop bit is 0
Parity error: parity mismatch
Break interrupt: all bits (including stop) are 0
Timeout: data in FIFO but no new data for counter_t cycles

内部信号：

名称	类型	位宽
`rstate`	reg	[3:0]
`rcounter16`	reg	[3:0]
`rbit_counter`	reg	[2:0]
`rshift`	reg	[7:0]
`rparity`	reg	-
`rparity_error`	reg	-
`rframing_error`	reg	-
`rbit_in`	reg	-
`rparity_xor`	reg	-
`counter_b`	reg	[7:0]
`rf_push_q`	reg	-
`rf_data_in`	reg	[`UART_FIFO_REC_WIDTH-1:0]
`rf_data_out`	wire	[`UART_FIFO_REC_WIDTH-1:0]
`rf_push_pulse`	wire	-
`rf_push`	reg	-
`rf_pop`	wire	-
`rf_overrun`	wire	-
`rf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]
`rf_error_bit`	wire	-
`break_error`	wire	-
`rcounter16_eq_7`	wire	-
`rcounter16_eq_0`	wire	-
`rcounter16_eq_1`	wire	-
`rcounter16_minus_1`	wire	[3:0]
`toc_value`	reg	[9:0]
`brc_value`	wire	[7:0]
`counter_t`	reg	[9:0]

子模块实例化：

实例名	模块名
fifo_rx	uart_rfifo

uart_regs.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_regs.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_regs`	module	0	0	UART Register File and Interru...

uart_regs¶

UART Register File and Interrupt Logic

Implements all UART16550 registers and interrupt management. Handles register read/write, baud rate generation, and interrupt priority encoding.

Registers

Addr	Write	Read	Name
0	THR	RBR	Transmit/Receive Buffer
1	IER	IER	Interrupt Enable
2	FCR	IIR	FIFO Ctrl / Interrupt ID
3	LCR	LCR	Line Control
4	MCR	MCR	Modem Control
5	-	LSR	Line Status
6	-	MSR	Modem Status
7	SCR	SCR	Scratch Register
0,1	DLH/DLL	DLH/DLL	Divisor Latch (DLAB=1)

Interrupt Priority

Receiver Line Status (highest)
Received Data Available
Transmitter Holding Register Empty
Modem Status (lowest)

内部信号：

名称	类型	位宽
`modem_inputs`	wire	[3:0]
`enable`	reg	-
`stx_pad_o`	wire	-
`srx_pad_i`	wire	-
`srx_pad`	wire	-
`wb_dat_o`	reg	[7:0]
`wb_addr_i`	wire	[`UART_ADDR_WIDTH-1:0]
`wb_dat_i`	wire	[7:0]
`ier`	reg	[3:0]
`iir`	reg	[3:0]
`fcr`	reg	[1:0]
`mcr`	reg	[4:0]
`lcr`	reg	[7:0]
`msr`	reg	[7:0]
`dl`	reg	[15:0]
`scratch`	reg	[7:0]
`start_dlc`	reg	-
`lsr_mask_d`	reg	-
`msi_reset`	reg	-
`dlc`	reg	[15:0]
`int_o`	reg	-
`trigger_level`	reg	[3:0]
`rx_reset`	reg	-
`tx_reset`	reg	-
`dlab`	wire	-
`cts_pad_i`	wire	-
`loopback`	wire	-
`cts`	wire	-
`cts_c`	wire	-
`rts_pad_o`	wire	-
`lsr`	wire	[7:0]
`lsr0`	wire	-
`lsr0r`	reg	-
`lsr_mask`	wire	-
`rls_int`	wire	-
`rda_int`	wire	-
`ti_int`	wire	-
`thre_int`	wire	-
`ms_int`	wire	-
`tf_push`	reg	-
`rf_pop`	reg	-
`rf_data_out`	wire	[`UART_FIFO_REC_WIDTH-1:0]
`rf_error_bit`	wire	-
`rf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]
`tf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]
`tstate`	wire	[2:0]
`rstate`	wire	[3:0]
`counter_t`	wire	[9:0]
`thre_set_en`	wire	-
`block_cnt`	reg	[7:0]
`block_value`	reg	[7:0]
`serial_out`	wire	-
`serial_in`	wire	-
`lsr_mask_condition`	wire	-
`iir_read`	wire	-
`msr_read`	wire	-
`fifo_read`	wire	-
`fifo_write`	wire	-
`delayed_modem_signals`	reg	[3:0]
`lsr0_d`	reg	-
`lsr1_d`	reg	-
`lsr2_d`	reg	-
`lsr3_d`	reg	-
`lsr4_d`	reg	-
`lsr5_d`	reg	-
`lsr6_d`	reg	-
`lsr7_d`	reg	-
`rls_int_d`	reg	-
`thre_int_d`	reg	-
`ms_int_d`	reg	-
`ti_int_d`	reg	-
`rda_int_d`	reg	-
`rls_int_rise`	wire	-
`thre_int_rise`	wire	-
`ms_int_rise`	wire	-
`ti_int_rise`	wire	-
`rda_int_rise`	wire	-
`rls_int_pnd`	reg	-
`rda_int_pnd`	reg	-
`thre_int_pnd`	reg	-
`ms_int_pnd`	reg	-
`ti_int_pnd`	reg	-

子模块实例化：

实例名	模块名
transmitter	uart_transmitter
receiver	uart_receiver

uart_rfifo.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_rfifo.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_rfifo`	module	0	0	Receive FIFO

uart_rfifo¶

Receive FIFO

16-deep synchronous FIFO for received data with error flag storage. Each entry is 11 bits: {break_flag, parity_error, framing_error, data[7:0]}. Provides overrun detection and error bit aggregation for LSR bit 7.

Parameters

fifo_width: 11 bits (8 data + 3 error flags)
fifo_depth: 16 entries

内部信号：

名称	类型	位宽
`data_out`	wire	[fifo_width-1:0]
`data8_out`	wire	[7:0]
`fifo`	reg	[2:0]
`top`	reg	[fifo_pointer_w-1:0]
`bottom`	reg	[fifo_pointer_w-1:0]
`count`	reg	[fifo_counter_w-1:0]
`overrun`	reg	-
`top_plus_1`	wire	[fifo_pointer_w-1:0]
`word0`	wire	[2:0]
`word1`	wire	[2:0]
`word2`	wire	[2:0]
`word3`	wire	[2:0]
`word4`	wire	[2:0]
`word5`	wire	[2:0]
`word6`	wire	[2:0]
`word7`	wire	[2:0]
`word8`	wire	[2:0]
`word9`	wire	[2:0]
`word10`	wire	[2:0]
`word11`	wire	[2:0]
`word12`	wire	[2:0]
`word13`	wire	[2:0]
`word14`	wire	[2:0]
`word15`	wire	[2:0]

uart_sync_flops.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_sync_flops.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_sync_flops`	module	0	0	Two-Stage Synchronizer

uart_sync_flops¶

Two-Stage Synchronizer

Reduces MTBF issues for asynchronous signal crossing. Two flip-flops in series with configurable reset and clock enable.

Usage

Used to synchronize srx_pad_i (serial receive input) and modem control signals (CTS, DSR, RI, DCD) to the clock domain.

内部信号：

名称	类型	位宽	说明
`sync_dat_o`	reg	[width-1:0]
`flop_0`	reg	[width-1:0]

uart_tfifo.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_tfifo.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_tfifo`	module	0	0	Transmit FIFO

uart_tfifo¶

Transmit FIFO

16-deep synchronous FIFO for transmit data buffering. Supports push/pop operations with overrun detection. Inferred as distributed RAM for FPGA efficiency.

Parameters

fifo_width: 8 bits
fifo_depth: 16 entries
fifo_pointer_w: 4 bits
fifo_counter_w: 5 bits

内部信号：

名称	类型	位宽
`data_out`	wire	[fifo_width-1:0]
`top`	reg	[fifo_pointer_w-1:0]
`bottom`	reg	[fifo_pointer_w-1:0]
`count`	reg	[fifo_counter_w-1:0]
`overrun`	reg	-
`top_plus_1`	wire	[fifo_pointer_w-1:0]

uart_top.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_top.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_top`	module	0	0	UART 16550 Top Level Module

uart_top¶

UART 16550 Top Level Module

Top-level wrapper for the UART 16550 compatible core. Instantiates the WISHBONE interface, register file, transmitter, receiver, and optional debug interface. Provides complete UART functionality including serial transmit/receive, modem control, and interrupt generation.

Architecture

WISHBONE bus interface (uart_wb)
Register file with interrupt logic (uart_regs)
Transmitter with TX FIFO (uart_transmitter + uart_tfifo)
Receiver with RX FIFO (uart_receiver + uart_rfifo)
Optional 32-bit debug interface (uart_debug_if)

Compatibility

WISHBONE rev B2
RS232 protocol
NS16550A compatible (mostly)

内部信号：

名称	类型	位宽
`stx_pad_o`	wire	-
`rts_pad_o`	wire	-
`dtr_pad_o`	wire	-
`wb_adr_i`	wire	[uart_addr_width-1:0]
`wb_dat_i`	wire	[uart_data_width-1:0]
`wb_dat_o`	wire	[uart_data_width-1:0]
`wb_dat8_i`	wire	[7:0]
`wb_dat8_o`	wire	[7:0]
`wb_dat32_o`	wire	[31:0]
`wb_sel_i`	wire	[3:0]
`wb_adr_int`	wire	[uart_addr_width-1:0]
`we_o`	wire	-
`re_o`	wire	-
`ier`	wire	[3:0]
`iir`	wire	[3:0]
`fcr`	wire	[1:0]
`mcr`	wire	[4:0]
`lcr`	wire	[7:0]
`msr`	wire	[7:0]
`lsr`	wire	[7:0]
`rf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]
`tf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]
`tstate`	wire	[2:0]
`rstate`	wire	[3:0]

子模块实例化：

实例名	模块名
wb_interface	uart_wb
wb_interface	uart_wb
regs	uart_regs
dbg	uart_debug_if

uart_transmitter.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_transmitter.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_transmitter`	module	0	0	UART Transmitter State Machine

uart_transmitter¶

UART Transmitter State Machine

Implements serial data transmission with configurable frame format. Supports 5-8 data bits, optional parity, and 1/1.5/2 stop bits. Reads data from TX FIFO and shifts out serially (LSB first).

States

IDLE -> POP_BYTE -> SEND_START -> SEND_BIT[x8] -> [SEND_PARITY] -> SEND_STOP -> IDLE

Features

Configurable word length via LCR[1:0]
Optional even/odd/mark/space parity via LCR[4:3]
1, 1.5, or 2 stop bits via LCR[2]
THRE (Transmitter Holding Register Empty) interrupt support

内部信号：

名称	类型	位宽
`tstate`	reg	[2:0]
`counter`	reg	[4:0]
`bit_counter`	reg	[2:0]
`shift_out`	reg	[6:0]
`stx_o_tmp`	reg	-
`parity_xor`	reg	-
`tf_pop`	reg	-
`bit_out`	reg	-
`tf_data_in`	wire	[`UART_FIFO_WIDTH-1:0]
`tf_data_out`	wire	[`UART_FIFO_WIDTH-1:0]
`tf_push`	wire	-
`tf_overrun`	wire	-
`tf_count`	wire	[`UART_FIFO_COUNTER_W-1:0]

子模块实例化：

实例名	模块名
fifo_tx	uart_tfifo

uart_wb.v¶

文件路径： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_wb.v

目录： /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/

模块列表¶

模块名	类型	端口数	参数数	概要
`uart_wb`	module	0	0	WISHBONE Bus Interface

uart_wb¶

WISHBONE Bus Interface

Handles WISHBONE protocol timing and data bus width conversion. Supports both 8-bit and 32-bit data bus modes. Inserts one wait state on all transfers and generates write/read enable signals.

Protocol

WISHBONE rev B2 compatible
Supports shared bus with wb_stb_i and wb_cyc_i
Byte selection via wb_sel_i in 32-bit mode
Input signal sampling for timing closure

内部信号：

名称	类型	位宽
`wb_dat_o`	reg	[7:0]
`wb_dat_i`	wire	[7:0]
`wb_dat_is`	reg	[7:0]
`wb_dat_o`	reg	[31:0]
`wb_dat_i`	wire	[31:0]
`wb_dat_is`	reg	[31:0]
`we_o`	wire	-
`wb_ack_o`	reg	-
`wb_dat8_i`	reg	[7:0]
`wb_dat8_o`	wire	[7:0]
`wb_adr_int`	wire	[`UART_ADDR_WIDTH-1:0]
`wb_adr_is`	reg	[`UART_ADDR_WIDTH-1:0]
`wb_we_is`	reg	-
`wb_cyc_is`	reg	-
`wb_stb_is`	reg	-
`wb_sel_is`	reg	[3:0]
`wb_sel_i`	wire	[3:0]
`wre`	reg	-
`wbstate`	reg	[1:0]
`wb_adr_int_lsb`	reg	[1:0]

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