SvDoc 项目摘要¶
文件数：13
模块数：11
模块统计¶
- interface: 1
- module: 10
模块列表¶
| 模块名 | 类型 | 端口数 | 参数数 | 文件 |
|---|---|---|---|---|
| raminfr | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/raminfr.v |
| uart_debug_if | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_debug_if.v |
| uart_if | interface | 1 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/if.sv |
| uart_receiver | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_receiver.v |
| uart_regs | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_regs.v |
| uart_rfifo | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_rfifo.v |
| uart_sync_flops | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_sync_flops.v |
| uart_tfifo | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_tfifo.v |
| uart_top | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_top.v |
| uart_transmitter | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_transmitter.v |
| uart_wb | module | 0 | 0 | /home/admin/.openclaw/workspace/projects/verification/UART-Verification-using-UVM/rtl/uart_wb.v |