综合脚本说明¶

#!/bin/bash
# synthesize.sh - 主综合脚本

# 设置环境变量
export DC_HOME=/eda/synopsys/dc
export PATH=$DC_HOME/bin:$PATH

# 运行综合
dc_shell -f synthesize.tcl | tee synthesize.log

# synthesize.tcl - 综合配置

# 读取设计
read_verilog -top chip_top ../rtl/chip_top.v
read_verilog ../rtl/cpu/cpu_core.v
read_verilog ../rtl/cache/icache.v
read_verilog ../rtl/cache/dcache.v

# 读取约束
read_sdc constraints/synthesis.sdc

# 设置综合选项
set_max_area 0
set_max_power 100mW

# 执行综合
compile_ultra

# 输出结果
write -format verilog -output output/chip_top_syn.v
write -format ddc -output output/chip_top_syn.ddc
write_sdc -output output/chip_top_syn.sdc

# 生成报告
report_area > output/area.rpt
report_timing > output/timing.rpt
report_power > output/power.rpt

# 运行综合
./synthesize.sh

# 查看报告
cat output/area.rpt
cat output/timing.rpt
cat output/power.rpt